CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today multi-media applications require at least an 8Mb and preferably even a 16Mb memory, which increases the relative cost of the memory system within a computer. In the near future, it is likely that 32Mb and 64Mb computers will become commonplace, which suggests a potential demand for 256Mb DRAMs (Dynamic Random Access Memory) and beyond. Still in the development stage, DRAMs in the Gigabit range are already under way, which necessitate the introduction of new techniques that guarantee the reliability of the product notwithstanding the added complexity to the design and manufacture of such memory devices. In view of the huge array size and lithographic difficulties that ensue, it is more important than ever to increase the chip yield. Process engineers are constantly attempting to reduce and ultimately, eliminate or mask defects. Faults that inevitably remain in the chip are generally eliminated using special circuit designs, and more specifically redundancy replacement.
The present invention is a novel configuration based on the concept of domains. The domains referred in the present invention are not bound by stringent, well defined boundaries. Certain domains may be large and encompass a plurality of memory arrays; others may be small in size, and encompass only portions of a memory array. Regardless of its size, each domain is provided with a number of redundancy circuits to replace faults located within the domain. By allowing an overlap between domains, it becomes possible to repair faults in a given memory array with any of the redundancy circuits positioned within the common area of the overlapping domains, provided the fault is found in the array being serviced by the two domains. Clearly, if the number of faults exceeds the number of redundancies available in the domain (or domains) servicing that array, the scheme will fail and the memory is not repairable. However, in accordance with the present invention, if all the redundancies within a first domain have been exhausted, unused redundancies present within another domain overlapping the first one are used as a means for repairing the remaining faults that were left out unserviced within the first domain.
Domains may be tailored to any size and may be arranged in any configuration. Domains can overlap each other or stand side by side. An advantage of overlapping domains is that such an architecture allows servicing faults located in areas common to both domains with redundancy elements positioned in either one of the two domains. This advantage is particularly important because repair means available within one domain may be, at a given time, fully exhausted, and the availability of a second, overlapping domain may, thus, be advantageously used to assist the first domain to complete the repair job left undone.
Several domains may be contained within one array or, alternatively, several arrays may be contained within one domain. In this manner, a designer can take greater advantage of a given domain configuration and a choice of sizes to optimize the repairability of the design.
Conventional redundancy configurations typically employ a Fixed Domain Redundancy Replacement (FDRR) architecture, wherein redundancy elements are used to replace defective elements within a fixed size domain for each row and column redundancy.
Various configurations within the FDRR architecture have been successfully implemented over the years. A typical FDRR configuration, commonly used for low density DRAMs is shown in FIG. 1a. Therein are depicted a plurality of redundancy units used for replacing defective elements within the fixed size domain and which are appended to each sub-array comprising the memory. Each redundancy unit (RU) includes a plurality of redundancy elements (REs), (e.g., two RE per RU are illustrated therein), which are used to repair existing faults (labeled X) within the corresponding sub-array. This scheme, known as intra-block replacement, increases the redundancy area overhead described herein after, as the number of sub-arrays increases for high density memories, since each sub-array includes a fixed domain for the replacement, and the domains in different sub-arrays are mutually exclusive of each other. This scheme requires at least one or, preferably, two RUs in each sub-array. Thus, the efficiency of the RUs is rather poor in view of its inflexibility which reduces the chip yield substantially when faults are clustered in a given sub-array. The above-mentioned scheme is described in an article by T. Kirihata et al., entitled "A 14 ns 4Mb DRAM with 300 mW Active Power", published in the IEEE Journal of Solid State Circuits, Vol. 27, pp. 1222-1228, Sept. 1992.
Another FDRR redundancy replacement arrangement, known as a flexible redundancy replacement configuration, is shown in FIG. 1b, wherein a memory is depicted having a single redundancy array as a large fixed domain of RUs to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU can repair faults (labeled X) located in any sub-array within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely, the redundancy array, having a certain number of RUs, may advantageously be used to service any number of sub-arrays forming the memory. This results in a substantial saving of area (also referred to as real estate) over the previous scheme, although it requires a substantial amount of additional control circuitry to properly service all the sub-arrays forming the memory.
More details regarding the above described configurations and the various trade-offs may be found in an article by T. Kirihata et al., "A Fault-Tolerant Design for 256Mb DRAMs", published in the Digest of Technical Papers of the 1995 Symposium on VLSI Circuits, pp. 107-108; in an article by T. Sugibayashi et al., "A 30 ns 256Mb DRAM with Multi-divided Array Structure", published in the IEEE Journal of Solid State Circuits, Vol. 28, pp. 1092-1098, Nov. 1993; and in an article by H. L. Kalter et al., "A 50 ns 16Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, Vol. 25, pp. 1118-1128, Oct. 1990.
In summary, a Fixed Domain Redundancy Replacement (FDRR) arrangement consists of a plurality of fixed-size domains, each of which can be independently used to replace faults contained within that domain. By expanding this concept to a chip, there may be found several domains, each having a fixed size and mutually exclusive of each other, to repair all the faults within the chip.
The FDRR architecture can be used in an intra-block replacement arrangement, wherein small domains make it possible to repair faults with minimum circuitry. However, such an arrangement is ineffective to repair clusters of faults. In the second FDRR arrangement, i.e., the flexible redundancy replacement architecture, large domains typical of such an architecture, provide good repairability of clustered faults. However, the circuit overhead is substantially increased--a significant disadvantage.
Flexible redundancy replacement is very effective in repairing a limited number of faults, especially if these faults affect bit lines, (either single bits or multiple bits); wordlines, (either single words or multiple words), and the like, all of which fall under the category of "hard faults". Yet, flexible redundancy replacement suffers from another distinct drawback in that it requires a significant number of RUs (and corresponding control circuitry) to overcome a second class of faults, known as "retention faults," in which a bit, stored in the capacitor that forms a DRAM cell, fades away over time in a weak cell, thereby producing a fault. This disadvantage is particularly troublesome because the number of retention faults far exceeds the number of hard faults.
Referring back to the hard faults within a memory, defects of this type tend to cluster. Accordingly, the intra-block replacement approach usually fails because of its poor flexibility. Hard faults are typically not too numerous, which can be ideally repaired with less RUs in a large domain. Flexible redundancy replacement is a good approach to repair hard faults, which can be serviced by a single large domain with less RUs. By way of example, if a domain contains four clustered defects, four RUs would be required to replace them in the domain. Designing four RU in each small domain with an intra-block replacement approach would require too much overhead. Even if this overhead would be acceptable, if, for instance, five clustered defects were present, the replacement of defects could potentially fail. In conclusion, increasing the domain size with the flexible redundancy approach is crucial to repair hard faults.
Retention faults, on the other hand, occur randomly throughout the memory, and their number is typically high; yet, there is a distinct advantage in that they occur randomly throughout the chip. For random faults, the intra-block replacement presents less drawbacks, because the faults are statistically distributed in many small sub-arrays. The intra-block replacement can repair a fault with less redundancy circuitry than that required for the flexible redundancy replacement. Clearly, if one RU were designed in each sub-array, with the purpose of detecting randomly occurring retention faults, then such a configuration would be ideal for detecting retention faults, provided at least one fault is present in the sub-array. Retention faults, on the other hand, are difficult to repair with a flexible redundancy replacement approach because of the large number of such faults, which frequently overwhelms the repair circuitry available in the memory device. Repairing too many faults with the flexible redundancy replacement approach is disadvantageous, because the flexibility approach requires an even greater overhead to repair such faults with the available redundancy circuitry.
In view of the foregoing, an important objective of an ideal redundancy configuration is to repair hard faults and retention faults, whether randomly distributed throughout the memory or clustered therein, without introducing an onerous burden caused by a complex redundancy area overhead. Typically, this overhead is divided into: a redundancy element overhead and redundant control circuitry overhead, both of which should be minimized to achieve good repairability and to maintain optimum performance of the memory.
Related redundancy replacement configurations, including some of the categories listed above, are described in the following references:
U.S. Pat. No. 5,491,664 to Phelan, issued Feb. 13, 1996, describes the implementation of a flexible redundancy memory block elements in a divided array architecture scheme. This configuration has both, the memory and redundancy memory blocks, coupled to a read bus to allow the redundancy memory in one memory sub-array to be shared by a second sub-array.
U.S. Pat. No. 5,475,648 to Fujiwara, issued Dec. 12, 1995, in which a memory having a redundancy configuration is described such that when an appropriate address signal agrees with the address of a defective cell, a spare cell provided by the redundant configuration is activated to replace the failing one.
U.S. Pat. No. 5,461,587 to Seung-Cheol Oh, issued Oct. 24, 1995, in which a row redundancy circuit is used in conjunction with two other spare row decoders, wherein by a judicious use of fuse boxes, signals generated by a row redundancy control circuit, make it possible to replace failing rows with spare ones.
U.S. Pat. No. 5,459,690 to Rieger at al., issued Oct. 17, 1995, describes a memory with a redundant arrangement that, in the presence of normal wordlines servicing defective memory cells, enables faulty memory cells to be replaced with redundant cells.
U.S. Pat. No. 5,430,679 to Hiltebeitel et al., issued Jul. 4, 1995, describes a fuse download system for programming decoders for redundancy purposes. The fuse sets can be dynamically assigned to the redundant decoders, allowing a multi-dimensional assignment of faulty rows/columns within the memory.
U.S. Pat. No. 5,295,101 to Stephens, Jr. et al., issued Mar. 15, 1994, describes a two level redundancy arrangement for replacing faulty sub-arrays with appropriate redundancy elements.
Whereas the prior art and previous discussions have been described mainly in terms of DRAMs, practitioners of the art will fully appreciate that the above configurations and/or architectures are equally applicable to other types of memories, such as SRAMs, ROMs, EPROMs, EEPROMs, Flash RAMs, CAMs, and the like.